Charge pumps are commonly used in flash and other types of solid state memory devices to provide voltages outside of the range of ground to the power supply voltage. In flash memory devices charge pumps are used to generate large negative voltages, such as -10 V, to erase memory cells.
A conventional eight stage charge pump using a four phase clock is illustrated in FIG. 1. The conventional charge pump system is comprised of eight charge pump stages 110-117, an output circuit 108, and a four phase clock generator 109. The four clock signals generated by clock 109 are labeled (.PHI.1, .PHI.1A, .PHI.2 and .PHI.2A. The eight charge pumps are connected in series so that the output of each charge pump provides a larger magnitude output voltage than the previous charge pump. The charge pump system of FIG. 1 is a negative charge pump system. Each charge pump stage 110-117 is comprised of a conventional charge pump circuit illustrated in FIG. 2. A circuit diagram of a conventional output stage 108 is illustrated in FIG. 3.
The charge pump system of FIG. 1 transfers negative charge from one charge pump stage to the next charge pump stage, and ultimately to NOUT 132. The system also transfers positive charge back through preceding charge pump stages to ground. The FIG. 2 charge pump circuit includes clock terminals OCK 220 and GCK 222, capacitor configured PMOS transistors P204 and P205 coupled to the clock terminals, PMOS pass transistor P201 coupled to IN 226 and OUT 224, and diode configured pull-down PMOS transistor P206. Referring to FIG. 2, when the clock signal coupled to OCK 220 goes high positive charge is coupled through the large capacitor formed by capacitor configured PMOS transistor P205 to node 224. Then the clock signal coupled to GCK 222 switches low and PMOS pass transistor P201 turns on. Positive charge is thereby coupled through transistor P201 and IN 226 to the preceding charge pump stage.
When the GCK 222 clock signal goes high, positive charge is coupled through the small capacitor formed by capacitor configured PMOS transistor P204. This positive charge increases the voltage of node 210 and turns off PMOS pass transistor P201. The OCK 220 clock signal then goes low which couples negative charge to node OUT 224. With transistor P201 off this negative charge is coupled to the next charge pump stage through OUT 224. This process of transferring positive charge to the preceding stage, and negative charge to the next stage is repeated at each charge pump stage. After a number of clock cycles, a negative output voltage is provided at NOUT 132.
The size of the output voltage that can be provided by conventional charge pump systems is limited by the increase in the threshold voltage of pass transistor P201. The threshold voltage V.sub.T for PMOS transistors increases with the bulk (substrate) to source voltage according to the equation V.sub.T =V.sub.TO -.gamma. (sqrt(.PHI.+V.sub.BS)-sqrt(.PHI.)), where V.sub.BS is the bulk to source voltage, V.sub.TO is threshold voltage for V.sub.BS =0, .gamma. is the bulk threshold parameter and .PHI. is the strong inversion surface potential. As the negative output voltage at each stage is increased the bulk to source voltage increases. As a result when the voltage at OUT 224 reaches a sufficiently large negative value, the decrease in the voltage at the gate of pass transistor P201, caused by a falling edge of the GCK 222 clock signal, becomes inadequate to turn on pass transistor P201. With pass transistor P201 off, the charge pump system is not able to use the preceding charge pump stages to drive the output current.
One technique for reducing the body effect is to reduce the voltage of the well coupled to the substrate terminal of pass transistor P201. Reducing the well voltage increases the magnitude of the output voltage that a charge pump system can provide. However, the body effect remains a problematic limiting factor. The constraints imposed by the body effect are particularly significant with low power supply devices.
Thus a low voltage charge pump system with a large output voltage range that overcomes the above problems of the prior art would be highly desirable.